The present invention relates to an apparatus, such as a magnetic disk apparatus for decoding a digital signal encoded and recorded by a partial response and a decoding method used in such an apparatus.
A magnetic recording channel in a hard disk or the like has a frequency response similar to that of an arrangement in which a differentiator and a low-pass filter are connected in series. In the magnetic recording channel, an intersymbol interference thereof is modeled as a partial response channel having an impulse response of 1-D.sup.2 or 1+D-D.sup.2 -D.sup.3.
In the magnetic recording channel in which the intersymbol interference is modeled by the impulse response of 1-D.sup.2, a binary code of 1 and 0 (or generally +a, -a) is outputted in the form of a ternary code of +1, 0 and -1 (or +c, 0, -c). A magnetic recording channel that is modeled by an impulse response of 1+D-D.sup.2 -D.sup.3 is referred to as "Extended Partial Response Class 4" (hereinafter simply referred to as "EPR4"). In this channel, the binary code of 1 and 0 (or generally +a, -a) is outputted in the form of a quinary code of +2, +1, 0, -1, -2 (or +2c, +c, 0, -c, -2c).
As described above, in the magnetic recording channel, the binary code is converted into a ternary or quinary signal due to the intersymbol interference. Therefore, it is necessary to decode a digital signal in such a manner that a binary code of 1 and 0 is generated from a ternary or quinary data symbol sequence.
The above-mentioned magnetic recording channel can be expressed as an arbitrary finite-state machine having N states (N=2.sup.m-1 is satisfied when m is the storage memory capacity of a convolutional code encoder). A two-dimensional graph in which the states (N number) of a certain time k of this finite-state machine are expressed by nodes arranged in the longitudinal direction and the transitions from the respective states to respective states of a time (k+1) are expressed by branches is generally referred to as "trellis diagram".
A Viterbi algorithm is used to search the shortest path on this trellis algorithm. The Viterbi algorithm becomes equivalent to a dynamic programming problem for optimization of a multistage decision process. A Viterbi decoder based on this Viterbi algorithm is adapted to estimate a transmission sequence in a certain band-limited channel having an intersymbol interference according to a maximum likelihood estimation. Specifically, the Viterbi decoder is adapted to select from a possible code sequence a code sequence which minimizes a distance metric (distance function) concerning a sequence of a received signal, such as a total sum of a square-error of a sequence of a received signal. In this sense, the Viterbi decoder has an error-correction capability. This Viterbi decoder generates and decodes a binary code of 1 and 0 from the above-mentioned ternary or quinary data symbol sequence.
As is well-known, the Viterbi decoder has complexities from a circuit standpoint, and it takes plenty of time for the Viterbi decoder to calculate data. The following paper has described a method of simplifying the circuit arrangement of the Viterbi decoder.
Reduced-complexity Viterbi Detector Architectures for Partial Response Signaling, G. Fettweise, R. Karabed, P. Siegel, and H. Thapar, GLOBECOM95, IEEE Cat. No. 0-78032509-5/95, pp. 559-563, Nov. 1995.
However, according to the method described in the above-mentioned paper, although the circuit arrangement of the Viterbi decoder can be simplified by the circuit system using the above-mentioned transformed trellis, there still remains such a problem that an operation speed cannot be improved. Incidentally, a patent that corresponds to the above-mentioned paper is a U.S. Pat. No. 5,430,744.
In the magnetic disk apparatus or the like using the above-mentioned Viterbi decoder, there is an increasing demand of increasing a storage capacity while maintaining a high rotational speed of a magnetic disk in order to effect a high-speed access. To this end, although it is necessary to raise a transfer rate at which data is transferred from a recording medium, there is then the problem that a low operation speed of the Viterbi decoder hinders a data transfer rate from increasing, thereby making it impossible to increase a storage capacity.
Furthermore, the following papers have described a method which can realize a high-speed operation of the Viterbi decoder.
Minimized Method Viterbi decoding: 600 Mbit/s Per Chip, Gerhard Fettweise, Herbert Dawid, Heinrich Meyr, IEEE 1990 Global Telecommunications Conference (GLOBECOM '90), pp. 1712-1716.
A 210 Mb/s Radix-4 Bit-level Pipelined Viterbi Decoder, Alfred K. Yeung. Jan M. Rabaey, 1995 IEEE International Solid-State Circuits Conferences. pp. 88-89, Paper WP 5.6, Slide Supplement pp. 68-69.
However, although the above-mentioned methods that had been described in the aforementioned papers can realize the high-speed processing of the Viterbi decoder, there still remains such a problem that the circuit arrangement of the Viterbi decoder becomes complex more than twice.
As a consequence, the whole of the apparatus such as the magnetic disk apparatus using the above-mentioned Viterbi decoder becomes expensive. Moreover, since the circuit arrangement of the Viterbi decoder has complexities as described above, an LSI (large-scale integration) package becomes large in size so that the apparatus using the Viterbi decoder cannot be miniaturized as it is expected.